Currently two classes of "flash" or bulk erasable EEPROMS using a floating gate structure are available: (1) those which require two power supplies, one for programming and another for reading; and (2) those employing a single relatively low voltage supply for all the programming, erasing and reading operations. When two power supplies are used, typically, a 12-volt power supply is used for programming and erasing, and a 5-volt power supply is used during read operations.
Devices employing a single, relatively low voltage power supply are disclosed in pending U.S. application Ser. Nos. 07/219,528 filed July 15, 1988, 07/219,529 filed July 15, 1988, and 07/219,530 also filed July 15, 1988. Programming and erasing are accomplished by Fowler-Nordheim tunneling through a thin dielectric window. Capacitive coupling between control gates and floating gates in the array is improved by extending the floating gate onto field oxide regions adjacent each cell. The extended floating gates provide increased coupling area with the corresponding overlying control gates.
Improved capacitive coupling allows programming and erasing at reduced control gate voltages. Additionally, during the read cycle, improved reading currents can be achieved. This is due to the fact that as the capacitive coupling is improved, a greater percentage of the voltage applied to the control gate can be coupled to the floating gate. This relationship is represented by the equation: EQU V.sub.f =KV.sub.g ( 1)
where
V.sub.f =voltage coupled to the floating gate. PA1 V.sub.g =voltage applied to the control gate. PA1 K=capacitive coupling ratio. PA1 C.sub.1 =capacitance between control gate and the floating gate. PA1 C.sub.2 =capacitance between floating gate and the source. PA1 C.sub.3 =capacitance between floating gate and the drain. PA1 C.sub.4 =capacitance between floating gate and the channel. PA1 C.sub.5 =capacitance between floating gate and the substrate.
The capacitive coupling ratio in floating gate structure non-volatile memories, is defined by: ##EQU1## where: C.sub.T =C.sub.2 +C.sub.3 +C.sub.4 +C.sub.5, and
From equations (1) and (2), it can be seen that if C.sub.1, the capacitance between the floating gate and the control gate, can be improved, then the capacitive coupling ratio will also be improved. Capacitance C.sub.1 can be improved if the coupling area between the control gate and the floating gate is increased.
Thus, a need has arisen for an electrically-erasable and programmable read-only memory cell with increased coupling area between the control gate and the floating gate. Such a cell will have the significant advantage of being programmable and erasable at reduced control gate voltages. Further, during the read cycle, improved read currents can be achieved for a given control gate voltage.